1. Field of the Invention
The present invention generally relates to an output buffer circuit. More specifically, the present invention is directed to such an output buffer circuit built in an integrated circuit, capable of suppressing power consumption caused by a penetration current of a CMOS transistor.
2. Description of the Related Art
In conventional logic ICs (integrated circuits) used in radio (wireless) appliances, a major subject is how to reduce noise contained in voltage signals derived from output buffers as low as possible. For instance, Japanese Patent Laid-open Application No. Hei-5-243957 published in 1993 describes one of this sort of conventional output buffer circuits.
FIG. 10 represents a circuit arrangement of the conventional output buffer circuit.
In this output buffer circuit, when a level of an input signal entered from the input terminal 88 is equal to an "L (Low)" level, namely is under normal state, a level of an output signal from the integrating circuit 87 becomes an "L" level. On the other hand, a level of an output signal outputted from the output terminal 83 becomes an "L" level. At this time, a level of an output signal outputted from the comparator 86 becomes an "H (High)" level, and a level of an output signal outputted from the NOT gate 80 becomes an "H" level. As a result, both a level of an output signal derived from the control circuit 84 constructed of the OR gate circuit, and a level of another output signal derived from the control circuit 85 constituted by the AND gate circuit become "H" level. Therefore, the p-channel MOS transistor 81 is turned OFF and the n-channel MOS transistor 82 is turned OFF, so that a level of an output signal outputted from the output terminal 83 becomes an "L" level.
Next, when the level of the input signal is changed from "L" into "H", the integrating circuit 87 gradually changes the level of the output signal from "L" to "H" in accordance with the time constant thereof. In such a case that the level of the output signal outputted from this integrating circuit becomes higher than the level of the output signal outputted from the output terminal 83, the level of the output signal derived from the comparator 86 becomes an "L" level, so that the p-channel MOS transistor 81 is turned ON, and also n-channel MOS transistor 82 is turned OFF. As a result, the level of the output signal outputted from the output terminal 83 is increased.
Then, when the level of the output signal derived from the output terminal 83 becomes higher than the level of the output signal derived from the integrating circuit 87, the signal of the output signal from the comparator 86 becomes an "H" level, so that the p-channel MOS transistor 81 is turned OFF. As a consequence, increasing of the voltage of the output signal derived from the output terminal is interrupted.
Furthermore, in the case that the level of the output signal derived from the integrating circuit 87 is increased and then this increased level of the output signal again becomes higher than the level of the output terminal 83, the level of the output signal from the comparator 86 becomes an "L" level, so that the level of the output signal outputted from the output terminal 83 is increased. In other words, in this conventional output buffer circuit, the level of the output signal derived from the output terminal 83 may follow the output signal of the integrating circuit 87. As a consequence, while the rapid increase of the output signal caused by the noise contained in the input signal is suppressed, the noise component contained in the output signal can be reduced.
However, in accordance with the above-explained conventional output buffer circuit, this output buffer circuit is designed based upon only the noise reduction in the output voltage, but not considering such an aspect that the power consumption caused by the penetration current of the CMOS transmitter is suppressed. This CMOS transistor is constructed of the p-channel MOS transistor 81 and the n-channel MOS transistor 82. In other words, the above-explained conventional output buffer circuit owns such a problem that the changing speed of the voltage is slow, and therefore, since a large amount of penetration currents will flow, the resulting power consumption is increased.